Both the register and net data types can be any number of bits wide if declared as vectors. Vectors can be accessed either in whole or in part, the left hand number is always the most significant number in the vector. See below for examples of vector declarations.
reg [3:0] output; // output is a 4-bit register
wire [31:0] data; // data is a 32-bit wire
reg [7:0] a;
data[3:0] = output; // partial assignment
output = 4'b0101; // assignment to the whole register
It is important to be consistant in the ordering of the vector width declaration. Normally the most significant figure is written first.
reg [3:0] a; // it is important to adopt one convention for
reg [0:3] b; // the declaration of vector width.
EXERCISE
a) Declare an 8 bit wire with variable name
address.
b) Assign 4'b1010 to its 4 most signficant bits.