TUTORIALS

Tutorial: Emerging Technologies

Presenter: Christof Teuscher, Portland State University, USA

Abstract:

The landscape of computing hardware, models, and systems is rapidly evolving for a number of reasons: manufacturing ever tinier conventional silicon electronics becomes harder and harder; reliability issues; the appearance of novel bio, nano, neuro, and hybrid devices; new application domains, system and design complexity beyond our capabilities; and the difficulty in programming systems to make them more robust, adaptive, and smart. However, there is little to no consensus in the research community on what type of technology, computing architectures, and computing paradigms hold most promises to address imminent and longer‐term challenges.

The goal of this tutorial is to provide a comprehensive and down‐to‐earth overview on emerging technologies in the area of computing hardware, models, and systems. I will outline the problems and grand challenges we face in the near and far term at each level, in particular in the topical area of the conference. I will provide in‐depth overviews of emerging technologies at the device, architecture, and system’s level with different time horizons. This will include nano, bio, neuro, and hybrid devices and systems. I will present these technologies in a very synergistic, interdisciplinary, micro‐ and macroscopic, and integrative way, at the common interface of computer engineering, computer science, physics, nano, bio, neuro, cognitive, and complex adaptive systems science.

Biography:

Christof Teuscher holds an assistant professor position in the Department of Electrical and Computer Engineering (ECE) at Portland State University and Adjunct Assistant Professor appointment in Computer Science at the University of New Mexico (UNM). He obtained his M.Sc. and Ph.D. degree in computer science from the Swiss Federal Institute of Technology in Lausanne (EPFL) in 2000 and 2004 respectively. In 2004 he became a postdoctoral researcher at the University of California, San Diego (UCSD), in 2005 a distinguished Director's Postdoctoral Fellow at Los Alamos National Laboratory, and in 2007 a Technical Staff Member. His main research interests include emerging computing architectures and paradigms, biologically‐inspired computing, complex & adaptive systems, and cognitive science. Teuscher has received several prestigious awards and fellowships. For more information visit: http://www.teuscher‐lab.com/christof

Tutorial: On-Die Calibration and Self-Correction Approaches for Reliable Clock Distribution Networks of High Performance Microprocessors

Presenters:

Cecilia Metra, University of Bologna, Italy

Simon Tam, Intel Corporation's Enterprise Microprocessors Group, USA

TM Mak, Intel Corporation's Sort/Test Technology Development Group, USA

Abstract:

The continuous scaling of microelectronic technology enable both IC performance improvement and higher level of integration. On the other hand, it also poses serious challenges to design, test and reliability. Increased operating frequency and SoC level of integration challenges every aspect of clock signal distribution (skew, duty-cycle, and short rise/fall time). The vast distribution of clock is also more aggravated by the increased probability of manufacturing faults and process variations. However, in a synchronous system, precise clock distribution is mandatory for correct system level functionality with the eventual application.

This tutorial will first discuss process variations and manufacturing faults which may affect clock distribution network of high performance processors and SoC, and describe their possible impact on the processor's operation. Then, we introduce on-die compensation, calibration and self-correcting techniques applied in modern designs, such as microprocessors and SoC, will be described. They allow: a) to compensate for process variations, b) to enable the IC to self-correct skews or duty cycle variations with the clock distribution network, either as a result of manufacturing faults or field degradation. The discussion will encompass industry wide techniques, as well as alternate, currently under development approaches.

Biographies:

Cecilia Metra is an Associate Professor in Electronics in the Department of Electronic, Computer Science and Systems (DEIS) of the Univ. of Bologna. She is also affiliated with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES) of the Univ. of Bologna. She has been Visiting Scholar at the Univ. of Washington, Seattle (USA) from 1998 to 2001, and Visiting Faculty Consultant for Intel Corporation, Santa Clara (CA) in 2002. She is Associate Editor in Chief of the IEEE Transactions on Computers, and a Member of the Editorial Board of the Microelectronics Journal, the Journal of Electronic Testing: Theory and Applications, and the International Journal of Highly Reliable Electronic System Design. She is the Program Chair of the IEEE Int'l VLSI Test Symp. 2009 and she has been Program Co-Chair of the IEEE Int'l VLSI Test Symp. 2008, the IEEE Int'l Workshop on Desing and Test of Nano Devices, Circuits and Systems 2008, the IEEE Int'l On-Line Testing Symp. 2005, 2004 and 2003, The IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems 1998, and the IEEE Int'l On-Line Testing Workshop 2002. She has been General Co-Chair of the IEEE Int'l On-Line Testing Symp. 2006, The IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems 2005 and 1999, and the IEEE Int'l On-Line Testing Workshop 2001, and Vice-General Co-Chair of the IEEE Int'l On-Line Testing Symp. 2007. She serves/served as Topic Chair for several international conferences, including the International Test Conference (ITC), the Design, Automation and Test in Europe Conference(DATE), the Design Automation Conference (DAC), the Great Lake Symp on VLSI (GLSVLSI), and the European Test Symposium (ETS),and she is/has been member of the Technical Program Committee of several international conferences, symposia and workshops. She has been/is responsible of Research Projects in collaboration with Intel Corporation (Santa Clara, CA; Hillsboro, OR; Austin, TX); STMicroelectronics (Agrate Brianza, Italia; Grenoble, France); Philips Research Labs (Eindhoven, The Netherlands); Alstom Transport (Bologna, Italy); Becar-Gruppo Beghelli (Bologna, Italy). Her research interests are in the field of Design and Test of Integrated Digital Systems, Reliable and Error Resilient Systems, Fault Tolerance, On-Line Testing, Fault Modelling, Diagnosis and Debug, Emergent Technologies. She published 149 papers in refeerred Journals and Conference Proceedings in these fields. She is a Golden Core member of the IEEE Computer Society and she received two Certificate of Appreciation and a Meritorious Service Award from the IEEE Computer Society.

Simon Tam received the BS, MS, & Ph.D. degrees in Electrical Engineering & Computer Sciences from the University of California at Berkeley. He is presently a Senior Principal Engineer at Intel Corporation's Enterprise Microprocessors Group, where he has been focused on the implementation of clocking circuits for the Xeon® MP Processors. Prior to microprocessor circuit designs, he was engaged with the development of neural network and non-volatile memory technologies. He has authored or co-authored in 38 technical publications and holds 28 US patents. He is a Senior Member of the IEEE and member of the Technical Program Committee for the 2007, 2008, & 2009 IEEE Symposium on VLSI Circuits.

TM Mak is an Engineering Manager with Intel Corporation's Sort/Test Technology Development Group, leading test methodology research. He has been with Intel for over 24 years and has worked on a variety of areas including test development, product engineering, design automation and design for test. He had served 2 terms to mentor MARCO/FCRP (Focus Center Research Program) research. He twice (1997 and 2004) received the SRC Outstanding Industrial Mentor Award. His current research interest ranges from defect based testing, fault effects as a result of nanometer technology, circuit level and physical design test issues, IO interface and analog testing, fault tolerant and on-line testing. He received the best paper award in 2004 International Test Conference and a best panel award from 2004 VTS. He currently holds 14 patents with 1 more pending. He had served on the program committees of various conferences and workshops. He is a Senior Member of IEEE and a graduate from Hong Kong Polytechnic University.

Tutorial: Fault Injection Techniques and Tools

Presenter: Massimo Violante, Politecnico di Torino, Italy

Abstract:

Designers of safety‐ or mission‐critical applications nowadays often rely in their systems upon commercial‐off‐the‐shelf (COTS) components (processors, memories, programmable devices, etc.) to meet the ever‐growing demands for resources and computing power coming from customers. Such components are not specifically designed for being fault tolerant, and therefore techniques are needed to validate the ad‐hoc error detection and correction techniques adopted in new COTS‐based systems aiming at critical applications. Fault injection is a popular technique that allows studying how systems behave in presence of faults, and therefore it can be used for debugging parts of new systems during the design phase, as well as validating the dependability of complete systems at the end of the design phase. The purpose of this tutorial is to introduce the audience to the concept of fault injection, outlining the typical structure of fault injection systems, then presenting some examples of tools available for running fault injection in complex, industry grade, designs. The tutorial will focus the discussion on the techniques developed in the last few years for evaluating the behavior of systems in presence of errors resulting from transient faults originated from ionizing radiation, it is therefore targeted to the aerospace community.

Biography:

Massimo Violante received the MS (1996) and PhD (2001) from Politecnico di Torino, Torino, Italy. Since 2001 he is with the Dept. of Computer and Automation Engineering at Politecnico di Torino where he is now Assistant Professor. Massimo Violante research activities focuses on the design and evaluation of mission‐critical systems, with particularly emphasis on the development of tools and techniques for enabling the use of commercial‐off‐the‐shelf (COTS) components in space.

He is involved in the following research activities:

1. Development of hardware‐assisted software‐implemented fault tolerance techniques for COTS processors use in space.

2. Development of fault‐injection techniques for COTS‐based computing systems using virtual platforms.

3. Development of software‐implemented fault injection techniques for COTS‐based computing systems.

4. Development of analysis techniques for FPGA‐based systems exploiting SRAM (rad‐hard and not rad‐hard) technology and Flash technology.

Massimo Violante lead a team of 5 persons within Politecnico di Torino, which is involved in a number of projects with several companies/agencies like Atmel, Boeing Satellite Systems, European Space Agency, and EADS. Massimo Violante authored one book on Software‐Implemente Hardware Fault Tolerance, and more than 130 papers on international journals and proceedings of international conferences.

Tutorial: Evolvable Hardware

Presenters:

Jim Torresen, University of Oslo, Norway

Lukas Sekanina, Brno University of Technology, Czech Republic

Abstract:

Traditionally, hardware has been static at run-time. However, with the introduction of reconfigurable technology and devices, dynamic hardware is now possible to realize by using automatic design schemes. One method for automatic design is evolvable hardware. The recent years of development of this field can be characterized as a continuous search for promising problems from the point of view of evolutionary design. In the first part of the tutorial, fundamental concepts of evolutionary circuit design and evolvable hardware will be introduced. Examples of evolved innovative designs will be presented in domains of small combinational circuits, middle-size circuits (such as image filters or arithmetic circuits) and large circuits (benchmarks for testability analysis methods), covering thus circuit complexity from a few gates to millions of gates. The second part will give an overview of the field targeting run-time evolvable systems. This includes an introduction of reconfigurable technology followed by a description of a number of the adaptable architectures that have been proposed. Challenges related to evolving systems in operation will also be addressed. A special focus will be given to the architectures designed for real-world applications.

Biographies:

Jim Torresen received his M.Sc. and Dr.ing. (Ph.D) degrees in computer architecture and design from the Norwegian University of Science and Technology, University of Trondheim in 1991 and 1996, respectively. He has been employed as a senior hardware designer at NERA Telecommunications (1996-1998) and at Navia Aviation (1998-1999). Since 1999, he has been a professor at the Department of Informatics at the University of Oslo (associate professor 1999-2005). Jim Torresen has been a visiting researcher at Kyoto University, Japan for one year (1993-1994) and four months at Electrotechnical laboratory, Tsukuba, Japan (1997 and 2000). His research interests at the moment include reconfigurable hardware, evolvable hardware, system-on-chip design and applying this to complex real-world applications. Several novel methods have been proposed. He has published a number of scientific papers in international journals, books and conference proceedings. He is in the program committee of more than ten different international conferences as well as a regular reviewer of a number of international journals (mainly published by IEEE and IET). He also acts as an evaluator for proposals in EU FP7.

A list and collection of publications can be found at the following URL: http://www.ifi.uio.no/~jimtoer/papers.html

Lukas Sekanina (MSc - 1999, PhD - 2002) received all his degrees from Brno University of Technology, Czech Republic. He was awarded the Fulbright scholarship and worked on the evolutionary circuit design with NASA Jet Propulsion Laboratory in Pasadena in 2004. He was a visiting lecturer with Pennsylvania State University and visiting researcher with Department of Informatics, University of Oslo in 2001. Lukas Sekanina is author of the monograph Evolvable Components (Springer Verlag, 2004). He co-authored more than 60 papers mainly on evolvable hardware. He has served as a program committee member of several conferences and received several awards for his work (including the Silver Medal at Humies 2008). Currently he is an associate professor and deputy head of the Department of Computers Systems at the Faculty of Information Technology, Brno University of Technology. Member of IEEE. For more information, see http://www.fit.vutbr.cz/~sekanina.

Tutorial: High Performance FPGA-based Bioinformatics

Presenter: Khaled Benkrid, University of Edinburgh, UK

Abstract:

Biological sequence analysis is an important field of computational science with many real world applications e.g. in disease diagnosis and drug engineering. It is also a field of study that is characterized by an exponential increase in the size of databases to be processed which outpaces the increase in computational power of general purpose processors. As a result, faster computer technologies are needed. Field Programmable Gate Arrays (FPGAs) have been proposed as a candidate technology to solve this problem as they promise the high performance and low power of a dedicated hardware solution while being reprogrammable. This tutorial will present the state-of-the-art of experiences in harnessing this technology in the important application of biological sequence analysis in particular, and Bioinformatics in general. The tutorial will also present the speaker’s own experience in developing highly parameterisable and efficient FPGA architectures for a number of sequence alignment algorithms including: Smith-Waterman, Needleman-Wunsch, and the BLAST algorithm. Experimental results suggest that FPGAs can be the implementation platform of choice for biological sequence analysis, especially with the advent of next generation sequencing technology.

Biography:

Dr Khaled Benkrid is a Lecturer in the School of Engineering at the University of Edinburg, Scotland, UK. During the last ten years, he has been actively researching the areas of high performance computing using reconfigurable hardware and electronic design automation. Among his early achievements in this area was the development of a structured FPGA design environment, called HIDE, which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL/Verilog. Dr. Benkrid also developed the pioneering concept of Hardware Skeletons as a way of satisfying the dual requirement of abstract high level design and hardware efficiency. The concept is being used successfully to develop highly parameterisable and efficient hardware architectures for high performance computing, with applications in digital signal processing, bioinformatics and computational biology, and scientific computing in general. Dr. Benkrid holds a PhD in Computer Science, a 1st Class “Ingénieur d’Etat” degree in Electronic Engineering, and an Executive MBA. He is Senior IEEE Member and a Chartered UK Engineer.