TUTORIALS

Tutorial: Self-Repairing and Tuning Reconfigurable Electronics: Real World Applications

Speaker: Didier Keymeulen, Jet Propulsion Laboratory

Abstract:

The Tutorial will address the applications of Self-Repairing and Tuning reconfigurable Electronics to two real world problems met by NASA.

The first application is related to radiation and extreme-temperature hardened electronics required by Space missions to survive the harsh environments beyond earth’s atmosphere. Traditional approaches to preserve electronics incorporate radiation shielding, insulation and redundancy at the expense of power and weight. The tutorial will show the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC). Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120ºC down to -180ºC). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180ºC) show the change over temperature of the response of the RAA for all possible bias voltage and demonstrate the feasibility of this approach.

The second application is related to inexpensive, navigation grade, miniaturized inertial measurement unit (IMU), which surpasses the current state-of-the art in performance, compactness (both size and mass) and power efficiency used by all NASA missions. The tutorial will explain a self-tuning method for reconfigurable Micro-Electro-Mechanical Systems (MEMS) gyroscopes based on evolutionary computation that has the capacity to efficiently increase the sensitivity of MEMS gyroscopes through tuning and, furthermore, to find the optimally tuned configuration for this state of increased sensitivity. We will present the results of an experiment to determine the speed and efficiency of an evolutionary algorithm applied to electrostatic tuning of MEMS micro gyros. The MEMS gyro used in this experiment is a pyrex post resonator gyro (PRG) in a closed-loop control system. A measure of the quality of tuning is given by the difference in resonant frequencies, or frequency split, for the two orthogonal rocking axes. The current implementation of the closed-loop platform is able to measure and attain a relative stability in the sub-millihertz range, leading to a reduction of the frequency split to less than 100 mHz.

Biography:

Didier Keymeulen received the BSEE, MSEE and Ph.D. in Electrical Engineering and Computer Science from the Free University of Brussels, Belgium in 1994. In 1996 he joined the computer science division of the Japanese National Electrotechnical Laboratory as senior researcher. Since 1998, he is senior member of the technical staff of JPL in the Bio-Inspired Technologies Group. At JPL, he is responsible for the applications of the DoD and NASA projects on evolvable hardware for adaptive computing that leads to the development of fault-tolerant electronics and autonomous and adaptive sensor technology. He is the test lead for the electronics of the tunable laser spectrum (TLS) instrument on the 2009 Mars Science Laboratory (MSL) mission to Mars. He served as the chair, co-chair, program-chair of the NASA/DoD Conference on Evolvable Hardware.

Tutorial: Run-Time Reconfigurable and Adaptive Hardware

Speaker: Jim Torresen, University of Oslo, Norway

Abstract:

Traditional hardware design aims at creating circuits which, once fabricated, remain static during run-time. This changed with the introduction of reconfigurable technology and devices (typically FPGAs) which opened up the possibility of dynamic hardware. However, the potential of dynamic hardware for the construction of self-adaptive, self-optimizing and self-healing systems can only be realized if automatic design schemes are available.

One such method for automatic design is evolvable hardware. Evolvable hardware was introduced more than ten years ago as a new way of designing electronic circuits. Only input/output relations of the desired function need to be specified, the design process is then left to an adaptive algorithm inspired from natural evolution. The design is based on incremental improvement of a population of initially randomly generated circuits. Circuits among the best ones have the highest probability of being combined to generate new and possibly better circuits. Combination is by crossover and mutation operation of the circuit description.

In this tutorial, an introduction to how reconfigurable logic can be applied in run-time reconfigurable systems will be given. Further, an overview how evolvable hardware can be applied to provide run time adaptivity will be included. Thus, this tutorial will give an introduction to run-time reconfiguration and adaptation of hardware and present what is state-of-the-art today.

Biography:

Jim Torresen received his M.Sc. and Dr.ing. (Ph.D) degrees in computer architecture and design from the Norwegian University of Science and Technology, University of Trondheim in 1991 and 1996, respectively. He was employed as a senior designer at NERA Telecommunications (1996-1998) and at Navia Aviation (1998-1999). At NERA he was involved in designing hardware for a digital power line carrier system. Hardware design was also undertaken at his position at Navia Aviation, where a satellite-based flight landing system was designed. Since 1999, he has been a professor at the Department of Informatics at the University of Oslo (associate professor 1999-2005).

Jim Torresen has been a visiting researcher at Kyoto University, Japan for one year (1993-1994) and four months at Electrotechnical laboratory, Tsukuba, Japan (1997 and 2000). His research interests at the moment include reconfigurable hardware, evolvable hardware, system-on-chip design and applying this to complex real-world applications. Several novel methods have been proposed. He has published 56 scientific papers (41 as the first author) in international journals, books and conference proceedings. He is in the program committee of ten different international conferences as well as a regular reviewer of a number of international journals (mainly published by IEEE and IET). He also acts as an evaluator for short proposals in EU FP7 FET Open.

A list and collection of publications can be found at the following URL: http://www.ifi.uio.no/~jimtoer/papers.html

Tutorial: State-of-the-Art of EDA Tools for Reconfigurable Systems Design

Speaker: Khaled Benkrid, University of Edinburgh, UK

Abstract:

This tutorial will present the evolution of Electronic Design Automation (EDA) tools for reconfigurable systems design since the early days of Field Programmable Gate Arrays (or FPGAs) technology. The speaker will present a variety of design languages and environments with a critique of each language/environment taking a number of considerations into account including programmer productivity, cost and implementation efficiency. The speaker will show how relentless advances in reconfigurable systems hardware are pushing for new tools and design methodologies drawing from experiences in high performance computing and software engineering.

In using and developing a variety of reconfigurable systems design tools, the speaker will finally present his views on the future direction(s) of EDA technology for reconfigurable systems design.

Biography:

Dr Khaled Benkrid has been a Lecturer in the School of Engineering and Electronics at the University of Edinburgh since February 1st 2007. Before that, he was a Lecturer in Computer Science at Queen's University Belfast. During the last ten years, Dr. Benkrid has been actively researching the areas of high performance computing using reconfigurable hardware and electronic design automation. Among his early achievements in this area was the development of a structured FPGA design environment, called HIDE, which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL/Verilog. Dr. Benkrid also developed the pioneering concept of Hardware Skeletons as a way of satisfying the dual requirement of abstract high level design and hardware efficiency. The concept has been successfully used in the design and implementation of a number of high level environments for FPGA-based digital signal co/processors.

Dr. Benkrid holds a PhD in Computer Science, a 1st Class “Ingénieur d’Etat” degree in Electronic Engineering, and an Executive MBA. He is Senior IEEE Member and a Chartered UK Engineer.