1.  Microfabrication Facilities at the Scottish Microelectronics Centre (SMC)

Institute for Integrated Micro and Nano Systems (IMNS)

Capability Profile

 

1.  INTRODUCTION

This document gives a brief outline of the Institute of Integrated Micro and Nano Systems' equipment base. This equipment and the research staff are located in theScottish Microelectronics Centre (SMC), a purpose built facility at the University's Science and Engineering campus at King's Buildings. The complex consists of approximately 250m²of class 10and 100m²of class 100 cleanrooms  and 1000m²of office and laboratory space. £6M of newequipment has been procured and the table 1 below gives a brief summary of equipment availability.

 

Equipment Type SEM	Wafer Size
	75mm	100mm	150mm	200mm
Furnaces(inc CVD Oxide/Nitride)	×	×	×	×
PECVD Oxide/ Nitride De position	×	×	×	×
ECR Oxide/Nitride Deposition	×	×	×	*
Metal Deposition	×	×	×	×
CMP	×	×	×	×
Photoresist Coat and Develop Tracks	×	×	×	×
Double Sided Aligner (MEMS)	×	×	×	×
W afer  Stepper Optical Lithography	×	×	×	×
e-Beam Lithography	×	×	×	*
Deep Etch (MEMS)	×	×	×	×
Ox ide Etch	×	×	×	×
Poly Etch	×	×	×	×
Metal Etch	×	×	×	×
XeF2 Etch	×	×	×	×
Surface Treatm ent	×	×	×	×
Anodic Bonding	×	×	×	×
Dicing Saws	×	×	×	×
Etch Release (critical point dryer)	×	×	*	*
Pary lene Deposition	×	×	×	×
Evaporation	×	*	*	*
FIB	-	-	-	-
SEM	×	×	×	*
AFM	×	×	×	×

Table 1. Equipment availability.

* Not available
×indicates availability

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If you would like to access some of these facilities or would like more details on the technologies available please contact Tom Stevenson (Tom.Stevenson@ee.ed.ac.uk), Anthony Walton (Anthony.Walton@ee.ed.ac.uk), Andrew Bunting (Andy.Bunting@ee.ed.ac.uk) or some other member of the IMNS located in the Scottish Microelectronics Centre (SMC).

Tom Stevenson
Institute of Integrated Micro and Nano Systems
Scottish Microelectronics Centre
School of Engineering and Electronics
Kings Buildings
University of Edinburgh
Edinburgh
EH9 3JF, UK
Tel:	0131 650 1000 ext 5622	(International +44 131 650 1000)
Tel:	0131 650 5622 (Direct dial)	(International +44 131 650 5622)
Fax:	0131 650 6554	(International +44 131 650 6554)
Tel:	0131 650 7474	Secretary
email:	Tom.Stevenson@ee.ed.ac.uk

Maps showing the location of the SMC inEdinburghand its position within theKings Building campusare available.

Photograph of the SMC building. The cleanrooms are the housed in the low portion of the building. The offices and laboratories are located in the four storey portion with the second floor consisting of space for rental by external organisations.

 

 

 

Central WIP corridor that provides access to the eight class 10 cleanroom bays.

 

 

 

Cleanroom bay before hookup of equipment. Each bay is serviced with DI, town and chilled water, nitrogen, compressed air, power, gases and vacuum.

 

2.  ENVIRONMENT

 

The cleanrooms are located in the purpose build £4.2M ScottishMicroelectronics Centre building. This class 10 facility comprises 250 sq metres is controlled to 21±1°C with a relative humidity of 40±5% with a raised floor being used as the air return to the plenum.

 

 

 

3.  WAFER FABRICATION EQUIPMENT

The Laboratories maintains the following major items of processing equipment.

DC Magnetron Sputter Coater

 

Balzers BAS450 coater system with two 5 in × 10 inch targets presently used for coating up to 24 × 3 inch wafer with Al/1%Si, Al,W and Ti. It is also capable of coating 4 and 6 inch wafers. Ion beam pre-cleaning is available using an Ion Tec Inc Kafmann source.

 

Oxford Plasmalab System 400 magnetron sputtering system capable of sputtering Al/1%Si, Al, W, Ta, Ti and TiN on 6 and 8 inch wafers. Ion beam pre-cleaning is also available.

 

 

Diffusion Furnace Tubes

Three quad stack Tempress Omega L furnaces, upgraded to direct digital control with supervisor computer. The systems are tooled for 3 inch wafers and support the following processes:

• Dry oxidation (with HCl gettering)
• Wet oxidation (burnt hydrogen with HCl gettering)
• Nitrogen anneals (6" available)
• Phosphorus deposition (solid source or POCl3)
• LPCVD of Polysilicon
• LPCVD of Silicon Nitride

200mm tubes are available for oxidation, LPCVD silicon nitride (inc low stress) and polysilicon (inc low stress)

Dielectric Deposition

• Oxford Plasma Technology ECR deposition of SiO2 and Nitride. (3-6 inch wafers)
• STS Miultiplex PECVD vacuum load-lock system configured for SiOx and low stress nitride. Capable of coating up to 8" wafers.

 

 

 

 

Dry Etching

• STS PF 508 barrel reactor for plasma ashing of photoresist from up to 150 wafers/run. (3-8 inch wafers).

• STS Multiplex load locked aluminium and polysilicon RIE etcher using SiCl4, and Cl2 chemistry (3-6 inch wafers). 

• Plasmatherm PK244O RIE system using Fluorine chemistry to anisotropically etch silicon dioxide and nitride from 20 × 3 in wafers/run. It can also be used to etch 4-8 inch wafers.

• STS Multiplex ICP - Load locked inductively coupled plasma etch system configured for deep Si etching. Capable of etching up to 8" wafers.

Chemical Mechanical Polishing (CMP)

• Presi Mecapol E460 polisher configured for 3-8 inch wafers.
• SVG 8600 series double sided 6 inch scrubber.

 

 

Wet Etching

Fume extracted class 10 laminar flow chemical stations permit safe cleaning of furnace quartzware and the processing of 3 to 8 in wafers in industry standard cassettes through the stadard mineral acid cleaning and etching treatments.Wafers are finally dried in Fluoroware or Tempress rinser/driers. A Maragoni dryer is also available(3-8")

 

 

Wafer Lithography

Photoresist coating, developing and baking are achieved on 3" a SVG 8600 track system and a CEE 75-200mm coater/develop system each comprising:

• Dehydration bake/ vapour prime, coat, hotplate softbake.
• Post exposur e bake, spray/puddle develop, hotplate hardbake.

 

Although facilities for negative resist processing are available, positive resist is the preferred patterning medium and the only one possible on the DSWs.

Mask aligning and exposure are carried out using contact printing or DSW (reduction projection printing) as appropriate. DSW printing is preferred for those chips greater than 6 mm square or those including geometries less than 3 microns. The machines in use are:

 

Contact printer : Cobilt 2020 soft contact (3")

Projection printer (double sided) : Karl Suss MA8/B6, (3, 4, 6 & 8")

Wafer Stepper: Optimetrix 8010, g-line, 0.32 NA, (3")

• 10X reduction stepper with 1.0 micron resolution over
• 1 cm square field and die by die alignment to ±0.3 micron.

Wafer Stepper: Optimetrix 8605, g-line, 0.32 NA, (3, 4 & 6")

• 5X reduction stepper with 1.0 micron resolution over
• 1.4 cm square field.

Wafer Stepper: Nikon Body 9, i-line, 0.57 NA, (6 & 8")

• 5X reduction stepper with 0.45 micron resolution over
• 2.2 cm square field.

4.  IN-LINE INSPECTION AND MEASUREMENT

Wafers are subject to visual inspection at all stages in processing using a variety of metallurgical microscopes from various manufacturers including Leitz, Reichart-Ju

ng, Olympus etc. In addition, linewidth measurements on masks and wafers are made to ±0.2 microns using a Biorad Coincident Shear System. Completed devices and wafers may be subjected to SEM analysis using a Htachi 4500 or whole wafers on a Philips E

E40FEG. Access to SEMs, FIB and an AFM is available through the Microelectronics Imaging and Analysis Centre (MIAC).

Profiling of wafer topography is available using a Dektak Model 8000 surface profiler to record step height variations in the range 0.01 to 60 microns.

Refractive index and thickness of visually transparent dielectrics such as silicon dioxide and silicon nitride are measured using an Applied Materials Ellipsometer model AME500 and a Sopra SE-5 Spectroscopic ellipsometer. This method is particularly useful in the thickness range 0.005 to 0.2 microns. Thicker dielectric layers and polysilicon layers are more readily measured using the Nanoscope Model 010-180 reflectometer.

Sheet resistance of large area process layers is measured using a Veeco 1000 4 point probe.

5.  ASSEMBLY

A low volume capability for the assembly of chips into Flat Packs, TO5 and Dual In-line packages is available using the following equipment:

• Dicing Saw - Disco 8" wafer chuck.
• Dicing Saw - Kulicke & Soffa Model 602M with 6" wafer chuck.
• Dicing Saw - Tempress Model 602M with 4" wafer chuck.
• Eutectic Die Attach - Dage-Precima Model EDB65 with mechanical scrub wetting.
• Wire Bond - Kulicke & Soffa Model 472 gold wire ultrasonic ball bonder.

Where devices may suffer degradation during eutectic die attach, low temperature processing is available using doped epoxy. Ultrasonic wire bonding provides the additional flexibility required for infrequent hybrid assembly jobs.

6.  OFF-LINE EVALUATION AND TEST

Capacitance/Voltage Testing

The HP4061 system runs an improved software package, EDUCATE, generated in-house, to determine the following:

• Low frequency CV
• High frequency CV
• Mobile ion concentration (temperature/bias)
• Interface trap concentration
• Impurity doping profiles in silicon

Parametric Testing

Two HP4062B test systems with 48 switchable pins are connected to a TAC automatic wafer prober which can be used to perform measurements required by IC-CAP and AURORA SPICE parameter extractors under software control. Similar measurements may also be made using HP4145 and HP 4156 semiconductor parameter analysers.

7.  DEVICE AND PROCESS SIMULATION

The Facility uses Ultra 10 SPARC workstations running with the UNIX operating system to give multi-user access to the Avant! process and device simulation packages. The following programs are available:

TWB	Design of Experiments
SUPREM-3	1-D Process simulation
TSUPREM-4	2-D Process simulation
MEDICI	2-D Device simulation
DAVINCI	3-D Device simulation
AURORA	Parameter extraction
DEPICT	Photolithography
TERRAIN	Etch and Deposition
MICHELANGELO	Gridder and data display
LAYOUT	Mask definition
RAPHAEL	Capacitance/resistance calculations
ICCAP	Parameter extraction
RS/1 Explore and Discover	Design of Experiments
Cornerstone	DOE and Statistical Analysis

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