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Title: Command & Control Buses as enabler for modular, reconfigurable spacecrafts:
present & future
Presenter:
Gianluca Furano, European Space Agency (ESA), Netherlands
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Summary:
Conventional space borne controls are based on Centralized Control systems
where a single CPU is responsible to control the application tasks, resulting
in high performance requirements for the CPU. Another downside of this system
is the physical concentration of I/O interfaces resulting in a great amount
of wiring and considerable impact on reliability and maintenance.
Established serial communication standards for space such as MIL-STD-1553B
and RS-485 are meant for Distributed Control architecture in form of
Master/Slave or Client/Server configuration. Nevertheless the above standards
are limited to the Media Layer definition, and, especially for 1553 case,
were optimized for systems with requirements very different from modern
spacecrafts, and lack a comprehensive and robust data layer standardization
that allows use of more modern and rapid prototyping, design, test and
integration techniques.
Since many years, Controller Area Network (CAN) and CANopen, a higher-layer
protocol based on CAN, represents the best choice for low-cost industrial
embedded networking.
Recognizing this, several European space missions have already opted for CAN
Bus as the Main On-Board Bus for their spacecrafts, subsystems or payloads.
These experiences have prompted ESA to drive a standardization process
resulting in recommendations to extend the CAN bus and CANOpen specification
to cover aspects that are required to satisfy special needs that have been
identified as being commonly required onboard spacecraft.
The experience of the use of CAN bus in terrestrial applications, such as
automobiles and factory process control, often in applications with demanding
safety and reliability requirements in hostile environments have been taken
into account when preparing the ECSS-E-ST-50-15C standard.
Those activities enable simpler architectures with obvious advantages in
terms of saving in wiring plus the increased capabilities of a distributed
intelligence system. Increased system reliability, improved service and
maintenance, higher autonomy, reduced downtime and reduced operating costs
are the prizes of this quest.
Biography:
Gianluca Furano, Physicist, PhD in Microelectronics, in ESA data system
division since 2003, chairs ECSS CAN bus standardization committee and is
contact point for MIL-STD-1553 in ESTEC. Supports avionic developments in
many ESA projects, like Alphasat, Exomars, ADM-Aeolus, VEGA, Ariane.
Title: Integrated System Health Management (ISHM): Enabling Intelligent Systems
Presenter:
Fernando Figueroa, NASA Stennis Space Center, USA
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Summary:
Integrated Systems Health Management (ISHM) is presented as an enabling discipline/technology area for intelligent systems. To that end, a variety of intelligent systems-relevant ISHM topics are addressed and examples presented. The information presented should provide the attendee with an understanding of current state, research, and challenges that are relevant to ISHM as a core capability of an intelligent system.
ISHM has been defined from many perspectives. Here it is defined as a capability that is achieved by integrating data, information, and knowledge (DIaK) that is conceptually and/or physically distributed throughout the system elements (which inherently implies the capability to manage DIaK associated with distributed sub-systems). This paradigm implies that DIaK must be available to any element of a system at the right time and in accordance with a meaningful context. ISHM Functional Capability Level (FCL) is measured by how well a system performs the following functions: (1) detect anomalies, (2) diagnose causes, (3) predict future anomalies/failures, (4) enable efficient integration and execution of all phases of the life-cycle of a system from a systems engineering perspective, and (5) provide the user with an integrated awareness about the condition of important elements of the system as a means of guiding user decisions.
Draft Tutorial Sections
1. Information architectures that enable representing complex systems as networked intelligent elements. For example typical propulsion systems might incorporate intelligent elements associated with physical entities such as intelligent sensors, intelligent valves, etc; but also intelligent process models that take place within physical elements and groupings of physical elements (e.g. a process model describing the pressurization of a nitrogen feed subsystem). DIaK must be managed throughout the intelligent elements.
2. Software environments that enable development of models of complex intelligent systems that support architectures embodying distributed intelligence (distributed management of DIaK).
3. Intelligent Sensors and Components as plug&play and interoperable network elements with embedded processing capability; embedded specifications; and ability to determine data quality (sensors) and their health using local DIaK, as well as with DIaK derived from complex processes on other network elements and systems.
4. Development, validation, and standardization of algorithms, methods, and approaches that help achieve ISHM functionality stated in the Background Section. For instance, determining noise level given a specific context in order to decide how to use measurements, or approaches to detect leaks which work for specified standard configurations, etc.
5. ISHM user interfaces that provide intuitive and rapid integrated awareness about configuration and condition of every element in a system.
6. ISHM integration with Systems Engineering Processes for development of advanced integrated systems/programs with embedded knowledge to achieve maximum safety and minimum cost throughout the life-cycle. This will be game changing for systems engineering processes, to achieve advanced systems that NASA needs for future explorations.
7. Current ISHM Implementations. Detailed example of an ISHM implementation at a rocket engine test stand (NASA Stennis Space Center).
Biography:
Fernando Figueroa has published substantially on ISHM in the last 10 years. He is considered a leading authority. He is reviewer of the NASA Fault Management Handbook currently under development, and is co-authoring a chapter of an AIAA book on Intelligent Systems (chapter on Intelligent ISHM). Dr. Figueroa has been selected to be the General Chair for the AIAA Infotech@Aerospace 2014 Conference.
Dr. Figueroa’s current and past roles include: lead PI on research and development projects involving NASA centers, industry, and universities. Technical Advisor to the Stennis Space Center-NESC Chief Engineer. Assistant to the Chief Engineer, Shuttle Systems and Integration, NASA Johnson Space Center . Areas of interest include Integrated System Health Management (ISHM), intelligent sensing systems, intelligent systems, robotics, controls, advanced sensors for rocket propulsion test..
Title: Adaptive Embedded System Design and Verification: Challenges & Solutions
Presenters:
Bhanu Kapoor (Mimasic),
Shireesh Verma (Conexant),
Prapanna Tiwari (Synopsys),
John Goodenough (ARM)
Summary:
Last year at the NASA/ESA AHS-2010, we presented a tutorial that focused on the fundamentals of the SoC power management design and verification. We looked into some of the key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi-Threshold CMOS (MTCMOS), and Active Body Bias (ABB).
We extend this tutorial to focus on both hardware and software design challenges of embedded systems that use these power management techniques. The use of above mentioned techniques also imply new challenges in validation of designs as new power states are created. We look into the characteristics of typical power states that exist in such designs and detail the techniques used in design validation. In majority of battery-operated applications, CPU spends most of its time in reduced power or sleep states. It is therefore critical that the embedded system offers an attractive selection of power states, wake-up sources, and start-up times so that the designers can optimize peripheral activities and recovery times to suit application requirements.
We look into some of the industrial examples providing a list of power states such as those offered by ARM and other processors and how these can be leveraged in adaptive embedded system design and related software development. We also take a look at some of the energy debugging aids that are available for the development of low power embedded software and highlight some of the key challenges that exist today in developing such systems.
Biographies:
Dr. Bhanu Kapoor is a consultant and owner at Mimasic, a consulting services company in the area of low power chip design and verification. He has played leading technology development roles at EDA startups ArchPro (now Synopsys), Atrenta, and Verisity (now Cadence). He started his career with Texas Instruments where he played various technical roles (1987-99) at TI’s R&D labs. He has helped set-up university technical advisory boards and played leading roles in joint industry and university research. Bhanu graduated from IIT Kanpur in 1987 with a degree in Electrical Engineering. He has received M.S. (1990) and Ph.D. (1994) degrees in Computer Science from SMU, Dallas. He is also an Adjunct Professor of Computer Science at SMU and serving as the Vice President of IIT Kanpur Alumni Association. He has authored over 30 IEEE/ACM conference/journal papers and has been granted 6 US patents in the area of low power design.
Dr. Shireesh Verma is a Senior Staff Engineer at Conexant. He has led several verification projects during his stints at Qualcomm Inc. and Marvell Semiconductor Inc. Mr. Verma obtained his PhD degree in functional verification from the University of California Irvine.
Prapanna Tiwari Prapanna Tiwari is a Staff CAE at Synopsys. He is responsible for verification solutions including planning, management, methodology and power-aware verification. Prior to Synopsys, he was at TI working on silicon reliability, power integrity, IR drop analysis and decap estimation. In 2005, he joined ArchPro Design Automation as one of the early employees developing dynamic and static low power verification solutions. He is currently based at Chandler, Arizona working for Synopsys on dynamic and static LP verification methodologies.
Dr. John Goodenough is responsible for all aspects of design methodology, including support for ARM's internal production and deployment. He also works extensively with ARM's design partners and customers. Dr. Goodenough began his career as a Sheffield University research fellow, investigating novel VLSI signal processing architectures. He then co-founded Infinite Designs, specializing in advanced ASIC and embedded system design methodologies. A board member of Accellera and Si2 and a founding member of SPIRIT, Dr. Goodenough has a B.S. from Durham University and a Ph.D. in VLSI design from Sheffield University.
Title: Building reconfigurable hardware for Space using commercial-off-the shelf FPGAs: challenges and possible solutions
Presenters:
Massimo Violante
Fernanda Lima Kastensmidt
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Summary:
The use of reconfigurable hardware in space is often advocated as the solution for fixing design bugs when the system is in orbit, for expanding the lifetime of systems already deployed in the field by improving year after year the functionalities it implements, and for boosting the execution of computing-intensive applications. For these purposes, reconfigurable field programmable gate arrays (FPGAs) are the enabling technology, as they offer an effective mean for implementing efficient user-customizable hardware that can be modified when the system is already deployed in the field. When facing the problem of selecting the best reconfigurable FPGAs for implementing reconfigurable hardware, designers have a number of choices with their advantages and disadvantages.
The purpose of this tutorial is to outline the problems arising from the use of reconfigurable FPGAs in space, and to present possible solutions. During the tutorial the following topics will be covered.
1. The impact of the space radioactive environment on re-configurable FPGAs (40 minutes)
a. The transistor-level point of view.
b. The circuit-level point of view.
2. Mitigation techniques for effective use of re-configurable FPGAs in space (50 minutes).
a. Hardening by design: the Atmel ATF280E case.
b. Hardening by architecture:
i. The Xilinx Virtex case.
ii. The Actel ProASIC case.
3. The key role of design tools (30 minutes):
a. Synthesis tool.
b. Place & route tools.
c. Validation tools.
Biography:
Prof. Massimo Violante received the MS (1996) and PhD (2001) from Politecnico di Torino, Torino, Italy. Since 2001 he is with the Dept. of Computer and Automation Engineering at Politecnico di Torino where he is now Assistant Professor. Massimo Violante research activities focus on the design and evaluation of mission-critical systems, with particularly emphasis on the development of tools and techniques for enabling the use of commercial-off-the-shelf (COTS) components in space. Massimo Violante leads a team of 6 persons within Politecnico di Torino, which is involved in a number of projects with several companies/agencies like Atmel, Boeing Satellite Systems, European Space Agency, and EADS. Massimo Violante authored one book on Software?Implemented Hardware Fault Tolerance, and more than 130 papers on international journals and proceedings of international conferences.
Dr. Fernanda Lima Kastensmidt received the BS (1997) in Electrical Engineering, MS (1999) and PhD (2003) degrees in Computer Science and Microelectronics from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. She is associate professor of Computer Science Department at the same university since 2005. Fernanda Kastensmidt research activities focus on radiation effects on programmable devices, fault tolerant techniques at circuit, architecture ad software levels for SEE mitigation. Her professional research experiences include internships in the Grenoble National Polytechnic Institute (INPG), France in 1999, in Xilinx Corporation, San Jose, USA in 2001, and in the Laboratory of Materials and Systems Integration (IMS) in Bordeaux University, France in 2008. Fernanda authored one book on Fault-?Tolerance Techniques for SRAM-? based FPGAs, published in 2006 by Springer, and more than 90 papers on international journals and proceedings of international conferences.
Title: Design of Analog-to-Digital Converters with Adaptive Resolution
Presenter:
M.B. Srinivas, Birla Institute of Technology and Science, India.
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Summary:
Analog-to-Digital Converters (ADC) are fundamental building blocks in mixed-signal VLSI circuits. Based on resolution, speed and power consumption, ADCs are classified into high speed [Flash, Semi-Flash and Pipelined] and low speed [SAR and Sigma-Delta] converters. Once an ADC is designed, its resolution and speed cannot be changed. While one can use a 12-bit precision from a 16-bit ADC, it is non-optimal resulting in low-speed of operation and extra power consumption due to full 16-bit internal operation. With the growing demand for wireless systems that can provide multi-standard services as a single-chip solution, there is a need to design a new class of ADCs that is capable of adapting to the required resolution while consuming less power. In this tutorial, fundamentals of ADCs and parameters used to characterize them are presented and techniques to design ADCs with adaptive resolution are discussed.
The tutorial will begin with a brief introduction to ADCs and a description of a variety of ADCs such as Flash, Pipelined, Successive Approximation and Sigma-Delta converters that are used in different applications. Parameters used to characterize these ADCs such as speed, resolution, INL, DNL, etc.. will also be described. Focus of the tutorial will be on techniques to design ADCs that have a truly adaptive resolution. These techniques have been developed by this author and his students over the last two years. It is shown how the proposed techniques also result in exponential decrease in power consumed by the ADCs while the resolution decreases linearly.
Biography:
Prof. M.B. Srinivas is currently a Professor of Electronics and Communication Engineering at the Birla Institute of Technology and Science, Hyderabad Campus, Hyderabad, India. His research interests are in high performance logic design, high speed and low power arithmetic circuit design and analog/mixed signal design, areas in which he has close to 100 publications. Prof. Srinivas is currently the Vice-Chair (Educational Activities), IEEE India Council. He was earlier the Chairman of IEEE, Hyderabad Section during 2007 and 2008 and was the student Activities Chair during 2002-2006. He is involved in organizing several international conferences including TENCON 2008 for which he was the General Co-Chair.
Title: Adaptive Sensing in Smart and Intelligent Sensor Systems
Presenter:
Sergey Y. Yurish, International Frequency Sensor Association, Spain.
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Summary:
An adaptation in smart sensors and sensor systems can be used for increasing of
measurement accuracy, decreasing of measuring time, power consumption reduction,
etc. The self-adaptation is relatively new function of smart sensors and sensor
systems. The proposed tutorial is based on a novel approach for self-adaptation
sensor systems design and devoted to advanced adaptive sensing with parametric
adaptation - a possibility to change accuracy to speed and conversely, and accuracy to
power consumption and conversely, depending on environment conditions and
measuring algorithm. The first type of parametric adaptation is intended for use in
critical applications when it is necessary to get measuring results as soon as possible.
The second type of parametric adaptation is intended to use in wireless sensor
networks, sensor nodes and embedded autonomous sensors, where power
consumption is a critical parameter. Both types of adaptation are possible due to
developed novel electronic component of sensor systems – programmable universal
sensor and transducers interface. This advanced integrated circuit is based on four
novel methods of measurements and is a core for the future integration platform for
smart, intelligent sensors and sensor systems. Main results, discussed in this tutorial
have been obtained during the European project ‘Smart Sensor Systems Design
(SMARSES)’ in the frame of Marie Curie Chairs Excellence (EXC) programme.
Practical examples of various intelligent sensor systems with self-adaptation
features will be given and discussed in details including novel, advanced methods,
metrological performances and design approach.
Biography:
Prof. Sergey Y. Yurish is a president of International Frequency Sensor Association
(IFSA) and Editor-in-Chief of Sensors & Transducers journal and IFSA Newsletter.
He has 25 years research experience in the field of smart sensors systems. He has got
his PhD degree in 1997. Dr. Yurish has published more than 160 papers and articles
in international conferences and peer reviewed journals, 5 books and holds 9 patents.
Prof. Yurish has got 3 best articles awards in 2007, 2008 and 2009, and 2 best papers
awards in 2009 and 2010. He is an IARIA Fellow 2010. It was granted to him for
continuous leadership roles and outstanding scientific research results. He is a
founder of Sensors Web Portal, Inc. (Canada) and co-founder of spin-off company
Technology Assistance BCNA 2010, S. L. (Spain).
Title: Catastrophic Damage from Total Dose in Space and Potential Recovery Methods
Presenter: Allan Johnston, JPL, USA
Summary:
This talk will be follow on to Allan Jonston's last year well received tutorial titled "Issues for Space Flight Electronics".
Biography:
Allan Johnston is a Principal Engineer at the Jet Propulsion Laboratory, specializing in applied research on radiation effects in electronic and optoelectronic devices for NASA space applications. Previous experience included more than twenty years at the Boeing Aerospace Company on radiation effects and reliability in microelectronics and aerospace systems, where he managed a research group on reliability, radiation effects, and fault-tolerant computing. He holds B.S. and M.S. degrees in physics from the University of Washington, Seattle, Washington.
His technical interests include ionization and single-event upset effects in semiconductor devices, with particular emphasis on low dose-rate effects, latchup, and applications of advanced technologies in space. Related interests include determining how new device technologies and device scaling will influence their radiation performance and reliability in space as well as radiation effects on optoelectronic devices. He is the author or coauthor of more than 90 papers in refereed journals, as well as a recent book, Reliability and Radiation Effects in Compound Semiconductors (World Scientific Press, April, 2010).
He received the Outstanding Paper award at the IEEE Nuclear and Space Radiation Effects Conference (NSREC) in 1999, Meritorious Paper Awards in 1994, 1995 and 1996, and the Distinguished Poster Paper award in 1987. Key publications include work on super-recovery (rebound) in MOS devices, latchup from single particles, dose rate effects in linear integrated circuits, the effects of device scaling on radiation susceptibility, and radiation effects in LEDs, optocouplers and laser diodes. He published invited papers on latchup in the IEEE Transactions on Nuclear Science (TNS) in 1996, on device scaling at the RADECS-1997 and RADECS-2002 Conferences, on optoelectronics in the TNS in 2003, and on radiation effects in microelectronics at the 2007 Integrated Reliability Workshop.
He has been active in the IEEE Nuclear and Radiation Effects Conference, serving as Short Course Instructor for four conferences, Local Arrangements Chairman, Short Course Chairman, and Awards Chairman. He was Technical Program Chairman for the 1997 NSREC, and General Chairman for NSREC in 2003. He is a Fellow of the IEEE.
He is the author of a book titled "RELIABILITY AND RADIATION EFFECTS IN COMPOUND SEMICONDUCTORS" .
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