Tutorials

Title: Issues for Space Flight Electronics

Presenter: Allan Johnston, JPL, USA

Summary:

This talk will focus on single-event upset effects in space, which can produce soft and hard errors in advanced microelectronics. It will begin with a brief summary of radiation environments, and then discuss the mechanisms for various SEE phenomena.

Specific examples will be discussed showing how fault tolerance can be used to mitigate these effect, including the use of those methods on an SRAM-programmable FPGA that was used in the landing sequence of the two Mars Exploration Rover missions.

The relationship between device scaling will be addressed, along with more recent examples of SEE phenomena in fielded space missions.

Although total dose effects are also important, it is not possible to include it within a talk of this length.

The outline of the tutorial will be as follows:

> Introduction

> Important Characteristics of the Space Environment
- Galactic cosmic rays
- Trapped protons in the earth’s environment

> Single-Event Effect Phenomena
- Basic characteristics
- Functional interrupt: the key problem for large-scale devices
- Effect of device scaling
- Effects in microprocesors

>System Approaches for Dealing with SEE
- Error-detection and correction
Example: Solid-state recorder on Cassini
- Latchup circumvention

>More Recent Examples
- Configuration SRAM for FPGAs on the Mars Exploration Rovers
- Clustered event in January, 2010

>Conclusions



Biography:

Allan Johnston is a Principal Engineer at the Jet Propulsion Laboratory, specializing in applied research on radiation effects in electronic and optoelectronic devices for NASA space applications. Previous experience included more than twenty years at the Boeing Aerospace Company on radiation effects and reliability in microelectronics and aerospace systems, where he managed a research group on reliability, radiation effects, and fault-tolerant computing. He holds B.S. and M.S. degrees in physics from the University of Washington, Seattle, Washington.

His technical interests include ionization and single-event upset effects in semiconductor devices, with particular emphasis on low dose-rate effects, latchup, and applications of advanced technologies in space. Related interests include determining how new device technologies and device scaling will influence their radiation performance and reliability in space as well as radiation effects on optoelectronic devices. He is the author or coauthor of more than 90 papers in refereed journals, as well as a recent book, Reliability and Radiation Effects in Compound Semiconductors (World Scientific Press, April, 2010).

He received the Outstanding Paper award at the IEEE Nuclear and Space Radiation Effects Conference (NSREC) in 1999, Meritorious Paper Awards in 1994, 1995 and 1996, and the Distinguished Poster Paper award in 1987. Key publications include work on super-recovery (rebound) in MOS devices, latchup from single particles, dose rate effects in linear integrated circuits, the effects of device scaling on radiation susceptibility, and radiation effects in LEDs, optocouplers and laser diodes. He published invited papers on latchup in the IEEE Transactions on Nuclear Science (TNS) in 1996, on device scaling at the RADECS-1997 and RADECS-2002 Conferences, on optoelectronics in the TNS in 2003, and on radiation effects in microelectronics at the 2007 Integrated Reliability Workshop.

He has been active in the IEEE Nuclear and Radiation Effects Conference, serving as Short Course Instructor for four conferences, Local Arrangements Chairman, Short Course Chairman, and Awards Chairman. He was Technical Program Chairman for the 1997 NSREC, and General Chairman for NSREC in 2003. He is a Fellow of the IEEE.

Title: Adaptive Power Management Architecture Design and Verification

Presenters:
Bhanu Kapoor (Mimasic),
Prapanna Tiwari (Synopsys),
John Goodenough (ARM), and
Amit Kumar (Sirf Technologies/CSR)

Summary:

We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for bulk of the semiconductor designs now. Power is a key reason behind the shift towards multi?core designs as increase in power consumption limits increases in clock speed at the rate we have seen in the past.

Voltage is the strongest handle for managing chip power consumption. Dynamic power is proportional to the square of supply voltage and leakage power has a linear relationship with it. In addition, leakage power has an exponential relationship with the threshold voltage of the device. This implies that if voltage can be controlled to optimally meet the performance then there can be much to be gained in terms of power savings.

This tutorial focuses on introducing fundamentals of the SoC power management design and verification to the attendees. We look in detail at some of key power management techniques that leverage voltage as a handle: Power Gating (PG), Power Gating with Retention (RPG), Multiple Supply Voltages (MSV), Dynamic Voltage Scaling (DVS), Adaptive Voltage Scaling (AVS), Multi?Threshold CMOS (MTCMOS), and Active Body Bias (ABB).

The use of above mentioned techniques imply certain power management architecture design and partitioning of design in terms of voltage islands that are controlled through power management signals. We look at the challenges in power management architecture design utilizing some examples that incorporate state?of?the?art power management techniques.

The use of above mentioned techniques also imply new challenges in validation of designs as new power states are created. We look into the characteristics of typical power states that exist in such designs and detail the techniques used in design validation. Techniques that leverage simulation, formal, and rulebased techniques are described in detail using examples. We make use of industrial design examples to aid explanation of these points. Facilities permitting, we will also add some hands?on examples for attendees to experiment with these issues utilizing latest developments in EDA tools.

Biographies:

Dr. Bhanu Kapoor is a consultant and owner at Mimasic, a consulting services company in the area of low power chip design and verification. He has played leading technology development roles at EDA startups ArchPro (now Synopsys), Atrenta, and Verisity (now Cadence). He started his career with Texas Instruments where he played various technical roles (1987?99) at TI’s R&D labs. He has helped set?up university technical advisory boards and played leading roles in joint industry and university research. Bhanu graduated from IIT Kanpur in 1987 with a degree in Electrical Engineering. He has received M.S. (1990) and Ph.D. (1994) degrees in Computer Science from SMU, Dallas. He is also an Adjunct Professor of Computer Science at SMU and serving as the Vice President of IIT Kanpur Alumni Association. He has authored over 30 IEEE/ACM conference/journal papers and has been granted 6 US patents in the area of low power design.

Prapanna Tiwari is a Staff CAE at Synopsys. He is responsible for verification solutions including planning, management, methodology and power?aware verification. Prior to Synopsys, he was at TI working on silicon reliability, power integrity, IR drop analysis and decap estimation. In 2005, he joined ArchPro Design Automation as one of the early employees developing dynamic and static low power verification solutions. He is currently based at Chandler, Arizona working for Synopsys on dynamic and static LP verification methodologies.

Dr. John Goodenough is responsible for all aspects of design methodology, including support for ARM's internal production and deployment. He also works extensively with ARM's design partners and customers. Dr. Goodenough began his career as a Sheffield University research fellow, investigating novel VLSI signal processing architectures. He then co?founded Infinite Designs, specializing in advanced ASIC and embedded system design methodologies. A board member of Accellera and Si2 and a founding member of SPIRIT, Dr. Goodenough has a B.S. from Durham University and a Ph.D. in VLSI design from Sheffield University.

Amit Kumar is a Senior Program Manager at SiRF Technologies. Mr. Kumar has been working in the field of digital IC design for more than 18 years managing and designing SoCs and ASICs for networking, wireless, and mobile applications with such companies as Philips Semiconductors, Intel, SiRF Technologies, C?DAC, and others. He has worked on micro?architectures, RTL design, processor?based SoC designs, high?speed designs, DfT, low?power design techniques, design?reuse, and on?chip busarchitectures.

Title: Building reconfigurable hardware for space using commercial-­off-­the shelf FPGAs: challenges and possible solutions

Presenter: Dr. Massimo Violante

Summary:

The use of reconfigurable hardware in space is often advocated as the solution for fixing design bugs when the system is in orbit, for expanding the lifetime of systems already deployed in the field by improving year after year the functionalities it implements, and for boosting the execution of computing-­intensive applications. For these purposes, reconfigurable field programmable gate arrays (FPGAs) are the enabling technology, as they offer an effective mean for implementing efficient user-­customizable hardware that can be modified when the system is already deployed in the field. When facing the problem of selecting the best reconfigurable FPGAs for implementing reconfigurable hardware, designers have a number of choices with their advantages and disadvantages.

The purpose of this tutorial is to outline the problems arising from the use of reconfigurable FPGAs in space, and to present possible solutions. During the tutorial the following topics will be covered.


1. The impact of the space radioactive environment on re-configurable FPGAs (40 minutes)
a. The transistor-level point of view.
b. The circuit-level point of view.

2. Mitigation techniques for effective use of re-configurable FPGAs in space (50 minutes).
a. Hardening by design: the Atmel ATF280E case.
b. Hardening by architecture:
i. The Xilinx Virtex case.
ii. The Actel ProASIC case.

3. The key role of design tools (30 minutes):
a. Synthesis tool.
b. Place & route tools.
c. Validation tools.

Biography:

Massimo Violante received the MS (1996) and PhD (2001) from Politecnico di Torino, Torino, Italy. Since 2001 he is with the Dept. of Computer and Automation Engineering at Politecnico di Torino where he is now Assistant Professor. Massimo Violante research activities focus on the design and evaluation of mission-critical systems, with particularly emphasis on the development of tools and techniques for enabling the use of commercial-off-the-shelf (COTS) components in space. Massimo Violante leads a team of 6 persons within Politecnico di Torino, which is involved in a number of projects with several companies/agencies like Atmel, Boeing Satellite Systems, European Space Agency, and EADS. Massimo Violante authored one book on Software?Implemented Hardware Fault Tolerance, and more than 130 papers on international journals and proceedings of international conferences.

Title: Adaptive Low Power and Energy Efficient System Design Techniques

Presenters:
Naehyuck Chang, Seoul National University.
Sachin Sapatnekar, University of Minnesota.
Lin Yuan, Synopsys.

Summary:

Energy and power consumption considerations have a growing impact on the performance, reliability, and cost of integrated systems. Advances in the semiconductor industry have brought forth many challenges and opportunities for low power and energy efficient system design. For a system designer, it is crucial to understand the factors that affect the power and energy consumption of today's systems, and to gauge the potential energy savings that can be gained from the available design techniques and EDA tools.

The goal of this tutorial is to bring the state-of-the-art in energy-efficient system design from the electrical design automation (EDA) community to the AHS audience. We will cover a broad range of topics: circuit-level techniques that consider manufacturing and process variation; fuel cell and battery hybrid system design; practical aspects of dynamic voltage scaling; chip temperature's impact on system performance, and temperature-aware low power methods.

Biographies:

Naehyuck Chang is a Professor in Dept. of Electrical Engineering and Computer Science, Seoul National University. His research interest includes low-power and embedded systems. He serves (and served) as Technical Program Committee EDA conferences such as DAC, ICCAD, ISLPED, DATE, CODES+ISSS, ASP-DAC, GLSVLSI and so on. He was a TPC chair of RTCSA 2007, ISLPED 2009 and ESTIMedia 2009. He is General Vice-Chair of ISLPED 2010 and TPC chair of ESTIMedia 2010. He is an Associate Editor of IEEE TCAD and ACM TODAES. He is a Guest Editor of ACM TECS and ACM TODAES for realtime multimedia systems and low power systems, respectively, in 2010. He served as the Chair of ACM SIGDA Low-Power Technical Committee for 2008 and 2009. He is ASP-DAC SIGDA Representative and ACM SIGDA Executive Committee Member (Technical Activity Chair). He is a Senior Member of ACM and a Senior Member of IEEE.

Sachin Sapatnekar is currently a Professor of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair and the Distinguished McKnight University Professorship. His current research interests lie in developing efficient techniques for physical design, timing, and simulation, as well as optimization algorithms. He has been an author/editor of eight books and has currently serves as Editor-in-Chief of the IEEE Transactions on CAD and General Chair for DAC 2010. He is a recipient of the SRC Technical Excellence Award and six conference best paper awards, and is a Fellow of the IEEE.

Lin Yuan is a Senior R&D Engineer at Synopsys Inc. in Mountain View, California. He is currently working on power network analysis and synthesis in design planning. His research interests include power integrity in physical design, power-driven synthesis, and thermal-aware design methods. He served as Publicity Chair at GLSVLSI 2007 and was on the Technical Program Committee for GLSVLSI in 2008 and 2009. He was a Session Chair at DAC 2009. He is an Associate Editor for the ACM SIGDA E-Newsletter. He received his B.S. degree in information engineering from Xi'an Jiaotong University, China in 2001, and Ph.D. degree in computer engineering from the University of Maryland, College Park in 2006. Dr. Yuan is a member of IEEE and a member of ACM SIGDA. He holds one U.S. patent in the area of power integrity.

Title: How Much Can I Trust the IC and Hardware?

Presenters:
Farinaz Koushanfar, Rice University.
Jim Plusquellic, University of New Mexico.
Mohammad Tehranipoor, University of Connecticut.

Summary:

With the increasing design complexity and the use of third party intellectual properties, integrated circuit (IC) and its design process need to be protected, secure, and trustworthy. How can I ensure that an IC or system designed and fabricated by others does not have any hardware Trojan inserted? Can I take any advantage of the IC to provide higher security? This tutorial will discuss the new challenges brought by the advanced IC design technologies to security and trust. We will also present several practical methods to detect hardware Trojan and to utilize circuit's unqiue characteristics during fabrication process for security purposes.

Two techniques are presented that leverage an IC's power grid for hardware security; one that is able to detect the presence of Trojan circuits by measuring the power supply current at multiple places on the power grid and a second that is able to produce a unique signature for each chip from power grid resistance variations that occur because of process variations.

Biographies:

Farinaz Koushanfar is an Assistant Professor of Electrical & Computer Engineering and Computer Science at Rice University, where she also directs the Texas Instruments DSP Leadership University Program. Before joining Rice in 2006, she received her Ph.D. in Electrical Engineering and Computer Science and her M.A. in Statistics both from the University of California, Berkeley. Her research is focused on developing techniques for synthesis and management of customizable, adaptive, lightweight, and secure embedded systems, adaptive energy delivery, and applications of emerging technologies. Koushanfar is a recipient of an Office of Naval Research (ONR) Young Investigator Program (YIP) Award, a National Science Foundation (NSF) CAREER Award, a Defense Advanced Research Projects Agency (DARPA) Young Faculty Award, an INTEL Open Collaborative Research (OCR) Fellowship, and a Mobicom Best Paper Award. In 2008, she was named one of MIT Technology Review's young innovators under 35 (TR-35).

Jim Plusquellic is an Associate Professor in ECE at the University of New Mexico. His research interests include IC trust, design for manufacturability, defect-based test, small delay fault test, model-to-hardware correlation, and process monitors. Dr. Plusquellic is on the program committees for the International Test Conference and the International Conference on Computer-Aided Design. He was General Chair of the Defect-Based Testing workshop in 2006, and he is currently the General Chair for the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust.

Mohammad Tehranipoor is currently an Assistant Professor of Electrical and Computer Engineering at the University of Connecticut. His current research projects include: computer-aided design and test for CMOS VLSI designs, design-for-testability, at-speed test, secure design and IC trust. Dr. Tehranipoor has published over 85 journal articles and refereed conference papers in the area of VLSI design, test, and hardware security and trust. He has published two books entitled “Nanometer Technology Designs – High-Quality Delay Tests” and “Emerging Nanotechnologies – Test, Defect Tolerance and Reliability” in addition to three book chapters. He is a recipient of a best paper award at the 2005 VLSI Test Symposium (VTS), best paper award at the 2008 North Atlantic Test Workshop (NATW), best paper award at NATW’2009, honorable mention for best paper award at NATW’2008, best paper candidate at the 2006 Design Automation Conference (DAC), best paper candidate at the 2005 Texas Instrument Symposium on Test, best panel award at VTS’2006, and top ten paper recognition at the 2005 International Test Conference (ITC). Dr. Tehranipoor is also a recipient of the 2008 IEEE Computer Society Meritorious Service Award, the 2009 NSF CAREER award, and the 2009 UConn ECE Research Excellence Award. He serves on the program committee of several leading conferences and workshops. Dr. Tehranipoor served as the guest editor for Journal of Electronic Testing: Theory and Applications (JETTA) and IEEE Design and Test of Computers. He served as Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T), Co-program Chair of the 2008 International Defect and Fault Tolerance in VLSI Systems (DFT), and General Chair for D3T-2009 and DFT-2009. He co-founded a new workshop called IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and Chair of Steering Committee. He is currently serving as an Associate Editor for JETTA, Associate Editor for IEEE Design and Test of Computers, Associate Editor for Journal of Low Power Electronics, and Editor for TTTC Newsletter. Dr. Tehranipoor is a term member of Graduate Faculty of ECE Department at Duke University. Dr. Tehranipoor is a Senior Member of the IEEE and Member of ACM and ACM SIGDA.