INVITED KEYNOTE SPEAKERS

Topic: Real world applications of adaptive and evolvable systems

Speaker: Tetsuya Higuchi, National Institute of Advanced Industrial Science and Technology, Japan

Abstract:

Dr. Higuchi is the leading figure in the real world applications of evolvable hardware. His speech will focus on semiconductor applications including analog LSI, clock timing adjustment, high-speed data transmission using the idea of evolvable hardware. While digital hardware design has made rapid progress due to advances in EDA software tools, analog hardware design is still highly reliant on the experience and maturity of analog hardware designers. It makes the applications of evolvable hardware in semiconductor become more and more important.

Biography

Tetsuya Higuchi heads the Evolvable Hardware Systems Laboratory in the National Institute of Advanced Industrial Science and Technology (AIST), Japan. He graduated from Keio University, Japan. After receiving Ph.D, he entered into Electrotechnical Laboratory (now AIST). In 2000, he also had a position of professor at University of Tsukuba. He heads the adaptive systems group at AIST. His interests are EHW, PLC and security systems.

Title: Neural Systems Engineering: brain-inspired computing

Speaker: Steve Furber, The University of Manchester, UK

Abstract:

The real-time modelling of large systems of spiking neurons is computationally very demanding in terms of processing power, synaptic weight memory requirements and communication throughput. We propose to build a high-performance computer for this purpose with a multicast communications infrastructure inspired by neurobiology. The core component will be a chip multiprocessor incorporating some tens of small embedded processors, interconnected by an NoC that carries spike events between processors on the same or different chips. The design emphasizes modelling flexibility, power-efficiency, and fault-tolerance, and is intended to yield a general-purpose platform for the real-time simulation of large-scale spiking neural systems.

The system will be adaptive with respect to both its fault-tolerance mechanisms and the natural adaptivity of the biological systems it is used to model.

Biography

Steve Furber is ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester. He received his B.A. degree in Mathematics in 1974 and his Ph.D. in Aerodynamics in 1980 from the University of Cambridge, England. From 1980 to 1990 he worked in the hardware development group within the R&D department at Acorn Computers Ltd, and was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor, both of which earned Acorn Computers a Queen's Award for Technology. Upon moving to the University of Manchester in 1990 he established the Amulet research group which has interests in asynchronous logic design and power-efficient computing, and which merged with the Parallel Architectures and Languages group in 2000 to form the Advanced Processor Technologies group. The APT group is supported by an EPSRC Portfolio Partnership Award. Steve is a Fellow of the Royal Society, the Royal Academy of Engineering, the British Computer Society, the Institution of Engineering and Technology and the IEEE.

Title: High-Performance Reconfigurable Computing the view from Edinburgh

Speaker: Rob Baxter, The University of Edinburgh, UK

Abstract:

This paper reviews the current state of the art in high-performance reconfigurable computing (HPRC) from the perspective of EPCC, the high-performance computing centre at the University of Edinburgh. We look at architectural and programming trends and assess some of the challenges that HPRC needs to address in order to drive itself across the chasm from the optimistic early adopters to the pragmatic early majority.

Biography

Rob Baxter is the Software Development Group Manager within EPCC at the University of Edinburgh. The Software Development Group comprises some 30 dedicated software developers who work on commercially-focused projects in novel and high-performance computing, from Grid software to industrial application optimisation. Dr Baxter has worked on industrial projects at EPCC since 1993, initially in a technical capacity and latterly in software project and research management. Recently he managed the successful £3.6M project which developed Maxwell, a 64-FPGA supercomputer based at EPCC, on behalf of the FPGA High-Performance Computing Alliance.

Title: Following the footsteps of others: Techniques for automatic shoeprint

Speaker: Danny Crookes, Queens University Belfast, UK

Abstract:

Shoeprint evidence is often left at scenes of crime, but is not always exploited. There is an increasing amount of research in developing systems to provide more rapid identification of footwear tread patterns. The need to identify scene of crime shoemark images, which can be very significantly degraded, is the real challenge. In this paper we review current approaches to this problem, and we present some novel methods and results for two different ways of addressing the problem - namely in the spatial domain and in the transform domain. In the spatial domain, improvements to existing techniques lead to two novel variations which we call the Modified Harris-Laplace (MHL) detector, and the enhanced SIFT descriptor. In the transform domain, we present results of a technique based on Phase-Only Correlation.

Biography

Danny Crookes became Professor of Computer Engineering at Queen’s University Belfast in 1993, and was subsequently Head of Computer Science for nine years. He is currently Research Director for Speech, Image and Vision Systems in the School of Electronics, Electrical Engineering and Computer Science. His research interests are in high performance image and video processing. Current research projects include: automatic shoeprint classification, analysis of ultra-large images for cancer diagnosis, and the design of high performance architectures and processors for image and video processing using FPGAs.