Column ADC's for High Resolution CMOS Imagers

CASE sponsored by STMicro-electronics.

CMOS image sensors have cost, size and power advantages over CCD image sensors due to the ability to integrate light sensing, signal processing and control functions on a single-chip. The front-end signal processing function on these sensors is an analogue-to-digital converter. It is the critical analogue block and often determines the power, frame rate and image noise.of the image sensor. The most traditional approach involves a column sampling array feeding a programmable gain amplifier and pipeline ADC. This technique has found success in low resolution imagers but does not scale favourably to higher resolution arrays. This is because the ADC is a bottleneck which must perform one conversion per pixel at the readout rate. As array size increases the readout rate decreases, bus capacitances and amplifier bandwidths increase. The power consumption and circuit noise quickly become excessive. Column-parallel ADC's place a single low rate converter in each column of the pixel array. The conversion rate of the ADC is greatly reduced by the parallelsim and is decoupled from image readout rate. This allows the ADC power consumption and noise bandwidth to scale very favourably with image array size. Column parallel ADC's using single slope conversion techiques are currently used in sensors with array sizes of up 1 megapixel. Maximum clock rates are around 48MHz which can be generated by a crystal oscillator without requiring an on-board PLL. As array size is increased beyond 1 megapixel, the clock frequency of the ADC becomes related to readout rate because of the line time available to generate the voltage ramp. Replacing single-slope conversion by a medium frequency conversion technique such as successive approximation or cyclic would llow ADC clock frequencies to be reduced. This will make the ADC drive components easier to design as well as allowing higher conversion resolutions (>10bits) to be achieved whilst preserving the optimum noise bandwidth properties. Techniques for medium speed conversion in column arrays must be investigated including shared and multiplexed column circuits. Use of latest process technogies (<0.18um) with multiple metal layers make more complex column circuits possible with efficient layout. High frequency digital readout circuits for the converted bits must also be investigated (e.g. SRAMs) to allow 30fps performance for multi-megapixel array sizes.

The primary point of contact for this work is Dr. David Renshaw